1. Field of the Invention
This invention relates generally to data processing systems and more particularly to a data processing system including a computer which has an external array of registers and includes an improved capability for parity checking.
2. Description of the Prior Art
Computer systems are often designed to include a large number of hardware registers that are used as data sources and destinations. These registers may contain status, interrupt, addresses, control bits for various parts of the computer, etc. In computer systems having a multi-byte data flow, these registers may be arranged as an external array of registers for addressing purposes, for example, an M.times.N array of registers. This is true even though the physical registers are located at many different locations within the system. The output of the registers can be assembled and fed into an arithmetic logic unit or a shifter input register where a parity check can occur. In many instances, it is desirable that an odd parity be maintained at the register data, which parity is checked at the arithmetic logic unit input register for the purpose of detecting machine malfunctions.
The particular organization of a register array may be influenced by the performance objectives and hardware limitations with the result being that there may be unimplemented bytes in the external register array. Such an unimplemented byte in the array will cause a parity check at the check point input because it will appear to be all zeros with even parity. In order to overcome this problem, it will be necessary to provide a parity bit for each vacant or unimplemented byte in the register array.
The concepts of parity checking and parity generating are well known in the computer industry. Typical prior art patents dealing with this situation are U.S. Pat. No. 3,342,983 and U.S. Pat. No. 3,986,015, both assigned to the same assignee as the present invention. U.S. Pat. No. 3,342,983 is primarily concerned with the situation where a parity error indication does not occur even though there has been an error, or in the situation wherein error indication occurs where in fact there has been no error. Accordingly, the patent is primarily concerned with the provision of arithmetic checking apparatus for indicating errors more accurately to eliminate the erroneous parity indications. U.S. Pat. No. 3,986,015 is primarily concerned with an improved method for generating parity check bits for data bytes resulting from an operation in an arithmetic unit. It utilizes parity bit generating circuitry which works on the uncorrected data appearing at the output of, for example, an arithmetic adder, but still provides the proper parity check bits for the corrected data which represent the final output for the arithmetic unit. However, neither of these prior art patents are specifically concerned with the problem of providing parity bits for vacant or unimplemented byte locations in an array of registers.
One approach to the solution of the problem might be to provide a single bit in each vacant byte in the array of registers. However, this would provide a very inflexible register configuration and, furthermore, would make it difficult to change the array whenever an error or problem existed in one of the implemented bytes in the array. Furthermore, it would be very difficult to run diagnostic problems using such a fixed bit format.